凯袁 is a skilled and versatile ASIC design engineer currently working at 英伟达 as a Senior ASIC PD Engineer since 2016. They are experienced in validating clock definitions, timing exceptions, and delivering timing layouts. Prior to this role, they worked at 上海兆芯集成电路有限公司 from 2014 to 2016 as an ASIC Design Engineer, where they managed GFX partition synthesis and optimization, ensuring high-quality outputs for tape-out.
Location
Shanghai, China
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