Rahul Kundu

Rahul Kundu is a seasoned DFT Engineer at NVIDIA since May 2021, having previously served as a DFT Architect at Intel Corporation from October 2011 to May 2021, where responsibilities included improving DFT methodologies and standards for Mixed Signal IPs. Kundu also contributed to the development of boundary scan insertion and validation flows for Intel's Hips and SoC products. Prior experience includes a role as a Component Design Engineer focused on DFT methodologies for mixed-signal hard IPs and a Staff CAD Engineer position at Intel from 2003 to 2011, where Kundu developed in-house ATPG tools and supported scan coverage debugging. Educational credentials include a B-Tech in Electronics and Communication Engineering from the Indian Institute of Technology, Kharagpur, a PhD in Computer Engineering from Carnegie Mellon University, and an MS in Computer Engineering from the University of California, Santa Cruz.