Rajat Bajpai is a Senior System Software Engineer specializing in Compute Compilers at NVIDIA, where employment commenced in August 2022 as part of the NVCC compiler team. Previous experience includes a role as a Trainee at the Department of Electronics and Information Technology in India in June 2014, followed by a position as a Software Engineer in R&D at Aricent from January 2016 to October 2017, focusing on Cloud Networking projects in collaboration with Intel's Data Center Group. Rajat also served as a Lead Software Engineer at Cadence Design Systems from October 2020 to July 2022, where significant contributions included the design and implementation of a SystemVerilog Nested Checker, alongside earlier work as a Software Engineer 2 on Cadence's Xcelium simulator. Educational qualifications consist of a Bachelor of Engineering in Electronics and Communications Engineering from Guru Gobind Singh Indraprastha University, achieved with First Class with Distinction, ranking in the top 5% of the graduating class, and prior studies at Andhra Education Society, where Rajat completed a Science stream with Computer Science.
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