Shirley Jiang

Shirley Jiang is a Senior Mixed-Signal Design Verification Engineer at NVIDIA, focusing on HBM design verification and the UPHY timing interface between analog and digital blocks. Previously, they worked as an Analog/Mixed-Signal Design Engineer at Marvell Technology, specializing in clock distribution for high-speed PHY IP and overseeing lab testing and characterization. Prior to that, at Synopsys Inc, they concentrated on receiver AFE circuits and provided mentorship to junior engineers while contributing to the development of internal EDA tools. Shirley earned a Doctor of Philosophy in Electrical and Electronics Engineering from the University of Alberta in 2019.