Tianlun Chen

Tianlun Chen is a Senior Design Verification Engineer at Nvidia, with professional experience in ASIC design verification for GPU IP and a strong background in computer architecture. Previously, Tianlun worked as a MTS Silicon Design Engineer at AMD from 2016 to 2025. Tianlun holds a Master's Degree in Electrical and Computer Engineering from North Carolina State University and a Bachelor's Degree in Electrical and Electronics Engineering from Hefei University of Technology. With comprehensive knowledge of UVM, SystemVerilog, and VLSI design, Tianlun specializes in reusable verification environments and memory architecture.