Tzon-Tzer Lu

Tzon-Tzer Lu is a highly experienced engineering professional with a solid background in mixed signal design and analog circuit design. Currently serving as a Manager and Senior Mixed Signal Design Verification Engineer at NVIDIA since June 2018, Tzon-Tzer specializes in chip-level mixed signal design verification. Prior experience includes a role as Senior Analog Design Engineer at MediaTek, focusing on CMOS analog circuit design with an emphasis on PLL design for Serdes/BT modem clock sources from March 2015 to June 2018. Tzon-Tzer's earlier positions include Engineer roles at Qualcomm and Hisilicon, with expertise in RF/Analog circuit design and Serdes circuit design, respectively. Tzon-Tzer holds both a Master of Science and a Bachelor of Science in Electrical and Electronics Engineering from National Taiwan University.