William Binder

William Binder is a Principal Static Timing Analysis and Methodology Support Engineer at NVIDIA, where they leverage their extensive experience in static timing closure, VLSI/ASIC design, and functional verification. With 20 years in the field, they previously held key positions at Qualcomm and IBM, where they led significant timing closure initiatives and methodological developments for advanced technology nodes. William's technical expertise encompasses a range of EDA tools and programming languages, and they have a proven track record of mentoring less experienced engineers and presenting complex information to diverse audiences. They earned a BS in Electrical and Computer Engineering from Worcester Polytechnic Institute.