Zheng Yan

Zheng (Zoe) Yan is a Senior Logic Design Engineer-FPGA at NVIDIA since December 2021, specializing in DGX FPGA logic design. Previously, Zheng worked at NVIDIA from July 2013 to June 2017 as an FPGA Engineer, completing multiple GPU and Tegra FPGA prototyping projects. Before that, Zheng served as an FPGA intern, focusing on FPGA synthesis, place and routing, and bitstream generation. From February 2018 to December 2021, Zheng was a Sr. ASIC/FPGA Hardware Engineer at Synopsys Inc., working on USB 3.1 and USB 3 projects. Zheng holds a Bachelor's degree in Communication Engineering and a Master's degree in Communication and Information Systems, both from Wuhan University of Technology.