Hareesh Boyilla has a diverse background in engineering, particularly in FPGA design and verification. From May 2022 to October 2023, Hareesh worked at Intel Corporation as an FPGA Design and Verification Engineer. Prior to this, Hareesh served as a Field-Programmable Gate Arrays Engineer at the Gas Turbine Research Establishment (GTRE), a part of DRDO, from March 2020 to August 2022. Hareesh is currently engaged with Oak Systems Private Limited since May 2024 in FPGA RTL design and verification. Earlier experience includes a role as an Embedded Software Engineer at BITECH Infosoft Private Limited from May 2018 to March 2020. Hareesh's educational background includes attending B.V.S High School from 2011 to 2015.
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