Ajay CS

Ajay CS is a Staff Analog Design Engineer at ONSEMI, where they specialize in VCO-based clock generator design, charge pumps, ramp generators, and various sophisticated circuit designs. With previous roles as an Analog Design Engineer II and Senior Analog Design Engineer at ONSEMI, Ajay has extensive experience in high-speed IO design and ESD clamps. Prior to that, they worked at Cypress Semiconductor Corporation and STMicroelectronics, focusing on high-speed IO circuits and Sigma-Delta modulators. Ajay is currently pursuing a Bachelor of Engineering in Electronics and Communications Engineering at Don Bosco Institute Of Technology.