Enze Chi

Enze Chi is an FPGA Engineer at Optiver Asia Pacific since 2019, specializing in RTL design and verification using SystemVerilog, Verilog, and VHDL. Previously, they held positions as a Senior Hardware Engineer at Blackmagic Design and a Senior ASIC/FPGA Design/Verification Engineer at Cisco, where they contributed to significant projects in line card design and verification. Enze also has experience as an ASIC Design Engineer at Beijing GuoXinAn Integrated Circuit Design Co., Ltd, working on CPU designs and security chips. Enze earned a Master’s degree in Microelectronics & Microsystems from UNSW in 2011.