Harry B. is an accomplished engineer with a strong background in FPGA design and low latency trading systems at Optiver since August 2022. Previously, Harry worked at Arm from September 2019 to August 2022, focusing on fetch-side design in SystemVerilog and formal verification. Earlier experience includes a role as a Software Engineer at HSBC, where Harry developed onboarding infrastructure for commercial banking clients using Java and Groovy. Harry holds a Bachelor’s Degree in Computer Science from The University of Manchester, completed in 2019.
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