Vikas Sooden is a seasoned engineer specializing in analog and mixed signal IC design, with a career that includes positions as Senior Principal Analog/Mixed Signal IC Design Engineer at Ouster, Principal Analog/Mixed Signal IC Design Engineer at Phoelex, and Principal Analog/RF Design Engineer at Agile Analog. Previous experience also includes a role as Principal Analog/Mixed Signal IC Design Engineer at Huawei Technologies Research & Development (UK) Ltd and as Senior Analog IC Design Engineer at Renesas, formerly known as Dialog Semiconductor.
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