Mayur Deshmukh

Mayur Deshmukh is currently an FPGA R&D Domain Specialist at Philips, with over 10 years of experience in FPGA design and validation. They have previously held positions as a Lead FPGA Design Engineer at Baker Hughes and a Senior FPGA Design Engineer at Siemens. Mayur's technical expertise spans various protocols and programming languages, including Verilog HDL and VHDL, alongside hands-on experience with multiple FPGA families and design tools. They earned an M.Tech in VLSI from Jaypee Institute of Information Technology and a Bachelor's degree in Electronics and Communication Engineering from Rajiv Gandhi Prodyogiki Vishwavidyalaya.