Yu Cheng Lin is a Digital IC Designer at Phison with a solid foundation in digital circuit design and verification. They have a notable history working as an Engineer and Senior Engineer at Realtek from 2011 to 2020, where they developed WiFi MAC layer features and led projects on new generation WiFi standards. Yu Cheng Lin also served as a Principal Engineer at Novatek from 2020 to 2022, focusing on SRAM BIST design and integration. They hold a Master’s degree in Electrical and Electronics Engineering from National Chiao Tung University and a Bachelor's degree from National Cheng Kung University.
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