Yilou Wang is a Verification Engineer at PlanV in Munich, specializing in RiscV and functional verification. They hold a Master of Science from the Technical University of Munich and a Bachelor's degree from Harbin Institute of Technology in China. Previously, Yilou completed internships at Infineon Technologies, where they focused on ESD testing and digital verification. They are also an official member of the Verilator GitHub Organization and an enthusiast of open-source projects.
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