Marek Palka

Marek Palka has extensive experience in the field of physics and hardware engineering. Marek is currently working as a Senior Digital Hardware Engineer at Positrigo since 2022. Prior to this, they worked at Paul Scherrer Institut PSI from 2020 to 2022, where they were a Physicist and FPGA Engineer. In this role, they worked on an algorithm for electron beam stabilization and was involved in various programming tasks using languages like Python, VHDL, C++, and Tcl scripts.

Before joining Paul Scherrer Institut PSI, Marek was an Assistant Professor at Jagiellonian University from 2004 to 2020. During this time, they played a leading role in designing and testing read-out and FEE electronics as part of the Positron Emission Tomography project. Marek also worked on the development of Boosted Decision Trees for particle identification and FPGA firmware for the L1Calo trigger system for the ATLAS experiment at CERN.

Additionally, Marek had short-term roles as a Corresponding Associate at CERN in 2016 and 2017. Marek also worked as a Visiting Researcher at Goethe University Frankfurt/Main from 2010 to 2011 and as a PHD Student at GSI Helmholtzzentrum für Schwerionenforschung from 2006 to 2010.

Marek Palka started their education at the Electronic Technical College in Sosnowiec in 1993 and completed their technician degree in Electronics in 1998. Marek then pursued a Master's degree in Electronics Engineering at the AGH University of Science and Technology from 1998 to 2003. Following this, Marek attended the AGH University of Science and Technology from 2001 to 2003, where they studied Physics without obtaining a specific degree. In 2003, they enrolled at Jagiellonian University, focusing on Physics, until 2005. Marek then continued their educational journey at Jagiellonian University, where they earned a Doctor of Philosophy (PhD) degree in Physics from 2005 to 2011.