Prem K.

Prem Koppala is a VLSI Design Engineer with expertise in Verilog/System Verilog, currently developing hardware architectures and focusing on functional correctness at Proxelera. They previously worked as a VLSI Design & Verification Intern at the same company. Prem earned a Bachelor of Technology in Electronics and Communications Engineering from Rgukt Nuzvid, completing their degree in 2024.