Steven Gartner

Steven Gartner has extensive experience in integrated circuit development, specializing in analog and mixed signal designs. They have held numerous roles, including ASIC Principal Layout Design Engineer at Qorvo, Inc. and Integrated Circuit CAD Engineer at Huawei Technologies, where they focused on layout, simulation, and verification. Educated in Aerospace Engineering and Electrical Engineering, Steven's career has spanned various companies, from Technical-Link N. America to Motorola Semiconductor, and includes expertise in EDA tools and PDK development. Currently, they continue their work in the cutting-edge field of high power analog integrated circuits.