ASHVINI SHARMA

Ashvini Sharma is a Senior Lead Design Engineer specializing in SoC/IP RTL design and architecture, with a strong emphasis on low power and high-frequency implementations. Ashvini has extensive experience in various complex IC architectures, including deep submicron designs and next-generation Gigabit Ethernet technology. Prior roles include Senior Design and Verification Engineer positions at Intel Corporation and Qualcomm, where Ashvini led cutting-edge technology projects focused on debugging and memory architectures. Ashvini holds a Bachelor's degree in Electronics and Communication from DR M G R Educational & Research Institute, completed in 2010.