Jagadeesh Kumar

Jagadeesh Kumar is a Lead RTL Design Engineer with over five years of experience in FPGA design, encompassing the full design cycle from requirement capture to hardware validation. Currently, they work at Qualcomm, where they have held roles as both Lead Engineer and Senior Engineer. Prior to this, Jagadeesh gained valuable experience as an FPGA Design Engineer at Data Patterns (India) Pvt Ltd from 2017 to 2021. They hold a Bachelor of Technology degree in Electrical and Electronics Engineering from the Universal College of Engineering & Technology, which they completed in 2017.