Jagadeesh Pujar is a highly experienced Sr Lead DFT Engineer currently working at Qualcomm since 2024. They previously held roles at Intel Corporation as a DFT Engineer from 2021 to 2024 and at GLOBALFOUNDRIES as a Senior Engineer (DFT) from 2018 to 2021. Jagadeesh possesses advanced skills in Verilog, System Verilog, MBIST, Scan Insertion, ATPG, and various design tools. They earned a Master of Technology in VLSI Design from the National Institute of Technology Goa in 2017, complementing an earlier Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from BIET Davangere.
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