Kunal Patil

Kunal Patil is a Senior Engineer at Qualcomm, specializing in writing RTL models in Verilog HDL and possessing a solid understanding of verification methodologies, particularly UVM. Kunal has past experience as a Trainee at Maven Silicon, where they gained hands-on experience with Verilog, System Verilog, and VLSI projects, and as an Associate Engineer at Samsung R&D. Kunal holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Sinhgad College of Engineering and a Master of Engineering in Communication from BITS Pilani, Hyderabad Campus.