Rajeev Ranjan is a highly experienced engineer specializing in physical design, with a significant background in implementing netlist to GDS processes for various advanced technologies. Currently serving as a Staff Engineer at Qualcomm since September 2021, Rajeev focuses on physical design for QDSP and NPU cores. Prior roles include Senior Lead Engineer at Qualcomm and Technical Lead at STMicroelectronics, where Rajeev worked on automotive MCUs using 28nm FDSOI technology. Earlier experience includes positions at Cadence Design Systems, Samsung Electronics, and a research internship at Karlsruhe Institute of Technology. Rajeev holds a Master of Science in Electrical Engineering and Computer Science from Seoul National University and a Bachelor of Technology from the Indian Institute of Technology, Roorkee.
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