Rajesh Dheenadayalan

Rajesh Dheenadayalan is a Lead Engineer at Qualcomm with over 9 years of experience in ASIC design and verification. They have demonstrated expertise in RTL design, SOC/block verification, and post-silicon validation, contributing to various projects across companies like SMSC, AMD, and MaxLinear. Rajesh holds an M.S. in Software Systems from the Birla Institute of Technology and Science and a B.E. in Electronics & Communication from the University of Madras. With proficiency in multiple serial protocols and advanced verification methodologies, they aim to excel as a leading ASIC design professional.