Saketh Pendyala

Saketh Pendyala is a Staff Engineer at Qualcomm with a Master's degree in VLSI Design and seven years of experience in ASIC physical design. Previously, they held roles at Soctronics, Samsung India, and Synopsys Inc, where they developed methodologies for low-power implementation and contributed to physical design processes. Saketh's educational background includes a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Nishitha College and intermediate studies at Siddhartha Junior College. They are focused on creating efficient design methodologies to enhance sign-off closure in full-chip and block executions.