Avinash Perumalla is an experienced engineer specializing in design for test (DFT) with a career spanning multiple companies. Starting as a Trainee at Maven Silicon in July 2019, Avinash moved on to an internship role before joining Cerium Systems as an Associate Engineer from April 2021 to April 2022, where responsibilities included working with subsystems comprising over seven blocks utilizing Synopsys and Tessent tools. Currently serving as a Senior DFT Engineer at Quest Global since December 2024, Avinash's design projects involve managing a design with approximately 500,000 flops, leveraging expertise in both Synopsys and Tessent tools. Academic qualifications include a Bachelor of Technology from KL University and outstanding performance in earlier schooling.
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