DINESH R.

Dinesh R. is a Senior Lead Engineer at Quest Global Engineering Services, currently leveraging 8 years of experience in Synthesis and Static Timing Analysis (STA). Dinesh specializes in timing closure, ECO implementation, and PPA optimization across several advanced technology nodes, including 2nm to 22nm. Previous roles include Design Engineer at Tessolve and Lead Engineer at Wipro, where Dinesh honed skills in industry-standard tools like PrimeTime and Design Compiler. Dinesh holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Sai Vidya Institute of Technology, where studies are ongoing. Passionate about semiconductor innovation, Dinesh is committed to solving complex timing challenges and optimizing performance.