Neelima V. is a skilled Physical Verification Engineer with a demonstrated history of working in the back-end flow of chip design. Currently serving as a Lead Engineer at Quest Global, Neelima has extensive experience in fixing DRCs, layout vs schematic discrepancies, and debugging at both block and sub-block levels. Previously, Neelima worked as a Design Engineer at ChipOnTime Technologies Pvt Ltd and as a Physical Verification Engineer at Wipro. Neelima is pursuing a Bachelor’s degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University, Kakinada.
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