PARTHIBAN K

Parthiban K is a skilled STA Engineer with extensive experience in RTL to GDS II flow and block level design implementation for advanced technology nodes, specifically 10 nm and 28 nm. From 2019 to 2022, they worked as a Physical Design Engineer at Altran, where they managed block level physical design with high cell counts and executed timing and functional ECOs. Currently, they are part of the STA team for Google clients at Tech Mahindra Cerium Pvt Ltd, overseeing signoff execution and timing closures for high-frequency blocks. Parthiban holds a Diploma in ECE, a Bachelor of Engineering in Electrical, Electronics and Communications Engineering, and a Master's degree in VLSI design.