Ranganathan Obli is an experienced engineering professional with a strong background in RTL and analog design. Ranganathan began a career as an RTL Design Engineer at SmartDV Technologies, contributing to the design of LIN and SENT Interface Controllers. After further experience as a High Speed Analog Design Engineer at GigaMicro Semiconductor, Ranganathan advanced to the role of Lead Analog Design Engineer at Cerium Systems, where work included designing regulators and a 1V bandgap reference while collaborating on various technology nodes. Ranganathan held positions as Technical Lead at SeviTech Systems Pvt. Ltd. and UST, and currently serves as Technical Manager at Quest Global. Ranganathan holds a Master of Science in VLSI System Design from M.S. Ramaiah School of Advanced Studies and a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Sona College of Technology.
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