TELLA SATISH

Tella Satish is a Physical Design Verification Engineer with proficiency in physical verification across N6 (TSMC) and I1278 (Intel) technology nodes. They worked at Capgemini Engineering from 2021 to 2024, where they implemented timing and functional ECOs and addressed various violations using industry-standard tools such as Calibre and ICV. Currently, Tella holds the position of Senior Physical Design Verification Engineer at Quest Global and has hands-on experience in backend flow processes, including floor planning and timing closure. They have a keen interest in ASIC development flow, physical design, and AI in chip design.