Michael Rahav

Michael Rahav is an experienced engineer specializing in FPGA and VLSI design. Currently employed at Radware as an FPGA Engineer since October 2023, Michael previously worked at Sequans Communications from January 2022 to October 2023 as a VLSI Design Engineer, focusing on ASIC design for complex cellular communication utilizing 5G NR technology for broadband IoT applications. Prior to that, Michael served as an FPGA Engineer at Agito Akribis Systems, where responsibilities included FPGA design for control systems, and at Phantom Technologies LTD, where the focus was on FPGA design for RADAR, drone detection, and jamming systems. Michael holds a Bachelor of Science in Electrical and Electronics Engineering from Afeka Tel Aviv Academic College of Engineering, completed in August 2020.