簡誌廷

誌廷 簡 is a Senior Analog Design Engineer at Realtek Semiconductor Corp., bringing 8 years of experience in analog circuit design with a focus on serdes IP design. Prior to this role, they worked at 瑞昱半導體股份有限公司 as an Analog Design Engineer, specializing in high-speed Serdes Design for Serial Link. They also gained valuable experience at 奇景光電, where they engaged in Serdes and PLL Design. 誌廷 holds a Master of Science in Electrical Engineering from 國立清華大學 and a Bachelor of Science in Electrical Engineering from 國立中正大學.