Chin Mun, Yew is a Senior Staff Packaging Design Engineer at Renesas Electronics since April 2022, with extensive experience in overseeing packaging design processes, marketability, and cost efficiency. Previously at IDT - Integrated Device Technology, Inc. from April 2013 to April 2022, Chin specialized in wafer-level CSP design and wire bond BGA substrate design, engaging in packaging design reviews and risk evaluations. Prior roles at Intel Corporation, Altera, Finisar Malaysia Sdn Bhd, Carsem (M) Sdn Bhd, and AT Engineering Sdn. Bhd. contributed to expertise in packaging solutions, substrate design, and technical mentoring. Chin holds a Bachelor of Engineering (Hons) in Electronics Engineering from Universiti Tunku Abdul Rahman and a Diploma in Mechatronics, Robotics, and Automation Engineering from Ungku Omar Polytechnic.
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