Jagdeep Singh

Jagdeep Singh is a seasoned professional in ASIC design with a decade of experience in the VLSI industry, specializing in micro-architecture, RTL design, and low power designs. Currently, Jagdeep is a Senior Staff Engineer at Renesas Electronics, focusing on the front-end design of next-generation automotive SoCs. Previously, they spent over six years at Qualcomm, where they held roles ranging from individual contributor to people manager, leading RTL development for CPU subsystems in Snapdragon SoCs. Prior to Qualcomm, Jagdeep worked at Analog Devices and Samsung Electronics, contributing to the design and verification of various digital signal processing components. Jagdeep holds a Master of Technology degree in Computer Systems Networking and Telecommunications from IIT Delhi.