Mark Chien

Mark Chien currently serves as the Design Verification Lead at Rivos Inc., specializing in pre-silicon design verification for DDR and HBM memory subsystems since May 2022. Previously held the position of Design Verification Director at FLC Technology Group, where Mark established a UVM framework verification environment and led verification efforts for DDR memory controller IP with various memory types and interfaces from July 2018 to May 2022. Earlier roles include being a Verification Lead for DDR memory at InnoGrit Corporation and a Design Verification Manager at Marvell Semiconductor, where Mark managed a team of over ten engineers while overseeing verification processes for DDR Memory Controller soft IP cores. Mark's technical foundation began with substantial experience as a Staff Verification Engineer and Senior Design Engineer at Marvell Semiconductor, focusing on mobile SOC compliance and ARM CPU core development. Mark Chien holds a Master of Engineering Science in Electrical Engineering and Computer Science from the University of Michigan and a Bachelor of Engineering in Computer Engineering from the University of Auckland.