Wei-Hsiang

Wei-Hsiang Ma is a highly experienced electrical engineer specializing in custom circuit design and standard cell library development. Currently working at Rivos Inc. since March 2023, Wei-Hsiang previously held the position of Stdcell Design Manager at TSMC from March 2016 to March 2023, where responsibilities included leading a team of approximately 40 people in standard cell PPA studies, optimization, and reliability analysis. Prior to that, Wei-Hsiang served as a Memory Design Engineer at Intel Corporation from September 2011 to February 2016, focusing on custom memory designs and bitcell analysis. Wei-Hsiang began the career as an intern at Advanced Micro Devices in 2006. Wei-Hsiang holds a Doctor of Philosophy (Ph.D.) and a Master's Degree in Electrical Engineering (VLSI) from the University of Michigan, a Master's degree in Finance and Banking from National Tsing Hua University, and a Bachelor's Degree in Electrical Engineering from National Taiwan University.