Veeresh K

Veeresh K is a Staff Design Verification Engineer at Samsung Semiconductor India Research (SSIR) with expertise in IP/SOC Verification and VIP Development. They have a total of 3 years of experience in modeling and verification, having previously worked for Mirafra Technologies and Western Digital, among others. Veeresh holds a B.Tech in Electronics and Communications Engineering and a Master of Technology in VLSI Design & Embedded Systems. Their technical skills include proficiency in System Verilog, UVM, C/C++, and various protocols, along with a strong ability to work collaboratively in global teams.