Jérémie DUTHIL

Jérémie DUTHIL has extensive work experience in the field of digital IC design engineering. Jérémie currently holds the role of Senior Digital IC Design Engineer at SCALINX since September 2020. Prior to this, they worked at REFLEX CES for a significant period from November 2015 to July 2020, where they served as an HDL Design Engineer, responsible for the development and integration of FPGA architecture on customized cards for clients. Jérémie also worked on complex cards with the latest FPGA technologies and interfaces. Jérémie had previously completed internships at REFLEX CES, where they gained experience creating VHDL/C IP implementing GigE Vision 2.0 and working as a web developer at imaload. Jérémie also worked as a quality controller at Mss Fnac for a brief period.

Jérémie DUTHIL's education history begins in 2010 when they enrolled at ESIEE Paris, where they pursued a Master's degree in Electronic Systems. During their time at ESIEE Paris, they focused on hardware and embedded software. Jérémie completed their Master's degree in 2015.

In 2014, Jérémie briefly attended KU Leuven, where they pursued a Master's degree in Electrical Engineering. Unfortunately, the duration of their studies at KU Leuven is not specified, but it can be assumed to be a short-term engagement.

Additionally, Jérémie DUTHIL also attended Université Paris-Est Marne-la-Vallée from 2010 to 2013, where they obtained a Bachelor of Science (B.Sc.) degree. Their field of study at the university revolved around Mathematics and Computer Science.