Sitaram Singh is a Senior Design Engineer at Qlar Group, formerly known as Schenck Process, since July 2024, having previously held the position of Design Engineer at Schenck Process from July 2022. Sitaram Singh holds an M.Tech in Machine Design and Analysis from NIT Rourkela, obtained in June 2022, and a Bachelor of Engineering in Mechanical Engineering from Rewa Engineering College, completed in June 2019. Sitaram Singh's educational background also includes a Higher Secondary degree in Science from Govt. Venkat Higher Secondary Excellence School No. 1 in Satna, Madhya Pradesh, and a High School degree from the same institution.
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