Stacey Secatch

Stacey Secatch has extensive experience in engineering and architecture, particularly in the development of Solid-State Drives and configurable networking solutions. Currently serving as Principal RISC-V Development and Architecture at Seagate Technology since February 2013, Stacey has held multiple roles including Principal Storage Engineer and Principal SSD Firmware Architect, focusing on hardware and firmware features for Enterprise-class SSDs. Prior to Seagate, Stacey worked at Xilinx as a Senior Staff Engineer, specializing in configurable networking and memory solutions for FPGAs, and at Agilent Technologies as a Member of Technical Staff, designing digital composition blocks for mixed-signal ASICs. Stacey holds a Master of Engineering in Computer Architecture from Colorado State University and a Bachelor of Science in Electrical Engineering from the University of Michigan.