Yaakov Farfel

Yaakov Farfel is a seasoned Design Verification Engineer with extensive experience across various companies in the semiconductor industry. Current employment is with Semidynamics since June 2025, focusing on design verification. Prior roles include Senior Design Verification Engineer positions at companies such as Qualcomm and Nexite, where responsibilities included full chip verification and building digital models of analog blocks. Experience also encompasses verification ownership at Intel Corporation and an emphasis on Specman/System Verilog integration at Valens Semiconductor and other firms. Education includes a Master of Science in Electrical Engineering with a specialization in Microelectronics from the Moscow Institute of Electronic Technology.