Jian Chen

Jian Chen is currently the SoC Verification Lead at SenseTime, where they lead a team focused on verifying the next-generation AI chip and developing a verification platform. With over nine years of experience in design verification engineering, Jian has a strong background in digital ASIC design verification, specializing in SOC and NOC verification. They possess proficiency in UVM, System Verilog, C/C++, and various peripheral protocols, and have successfully contributed to several multinational corporations, including Qualcomm and Intel. Jian holds a Master of Engineering in Electrical and Electronics Engineering from Tongji University.