Vikrant Sharma is a Lead Design Engineer at Siemens, where they currently apply their extensive expertise in engineering design. Previously, they worked as a Design Engineer at Cyient, contributing to significant projects including BNSAR Phase 7 and Gresty Lane Resignalling Phase 2. Earlier in their career, Vikrant held positions as a Design Engineer at RRES and as a Signal Engineer at Atkins, where they focused on projects such as the East Kent Phase 2 and various designs across the UK. Vikrant earned a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Maharshi Dayanand University.
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