Gabriel Tarr

Gabriel Tarr is a Senior Staff Engineer at SiFive, specializing in power management features with over 20 years of experience in digital logic design. Previously, Gabriel worked as an MTS Design Engineer at AMD, focusing on Geometry Engine RTL design for RDNA 2-4 products, and as a Staff Engineer at Qualcomm, where responsibilities included RTL design for power management functions in custom server-class ARM CPU cores. Earlier in their career, as an Advisory Engineer at IBM, Gabriel engaged in VLSI development with VHDL and simulation in cycle-sim environments. Gabriel holds a Bachelor of Science degree in Computer Engineering from Rensselaer Polytechnic Institute.