Jeffrey (Liang Yu) Lin is a Design Verification Engineer currently serving as a Sr. Staff Design Verification Engineer at SiFive since 2025. Previously, they held positions as a Principal Engineer and Senior Principal Engineer at NXP Semiconductors from 2019 to 2025. Jeffrey's early experience includes an Engineering Internship at Broadcom Limited in 2007 and various roles in ASIC Design Verification at Marvell Semiconductor from 2014 to 2018. They earned a Bachelor of Science and a Master of Science in Electrical and Electronics Engineering, as well as pursuing a Ph.D. at National Chiao Tung University from 1994 to 2007.
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