Rajesh V.

Rajesh V. possesses extensive experience in engineering, primarily in the fields of FPGA and ASIC design, spanning over a decade. Currently serving as Senior Director of Platform Engineering at SiFive since May 2018, Rajesh previously held roles such as Director of Platform Engineering and Principal Engineer at Velodyne LiDAR, focusing on FPGA design for Lidar sensors aimed at autonomous vehicles. Prior to that, positions included Principal Engineer at Cryptography Research, where responsibilities included ASIC design and maintenance of CryptoManager IP, and various roles at LSI Corporation, SanDisk, Rambus, and GDA Technologies involving FPGA validation, memory controller verification, and Ethernet IPs. Rajesh holds an M Tech in Electrical, Electronics, and Communications Engineering from Vellore Institute of Technology and a BE in Electronics and Communication Engineering from the University of Madras.