Richard van

Richard Van is a highly experienced professional in microprocessor design and architecture, currently serving as Senior Director and Cache Subsystem Design Leader at SiFive since February 2022. Prior roles include Chief CPU Architect and Director at Futurewei Technologies, where RISC-V CPU research and development was led, and Principal Engineer/CPU Microarchitect at Spreadtrum Communications, focusing on ARM 64-bit high-performance CPU development. Previous positions at Soft Machines, NVIDIA, Sun Microsystems, and Intel Corp. contributed to expertise in L2 cache design and memory management. Richard Van holds a BS in EECS from the University of California, Berkeley, an MS in EECS from Santa Clara University, and a degree in Stanford Advanced Project Management from Stanford University.