Zhen Wei

Zhen Wei is a Staff Performance Architect at SiFive, with experience dating back to February 2020. During tenure at SiFive, Zhen contributed significantly to the performance model in Mid-Core and LSU units, progressing from a Senior Engineer to a Junior Engineer, focusing on RISC-V Vector hardware and software. Prior experience includes a role as a Research Assistant at National Taiwan University under Dr. Wei-Chung Hsu and an internship at Andes Technology Corporation, where Zhen modeled branch prediction policies for RISC-V cores. Zhen holds a Master's degree in Computer Science from National Taiwan University and a Bachelor's degree in Transportation Science from National Cheng Kung University.